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Austin, Texas — About a year ago, University of Florida professor Jerry Fossum took a sabbatical to work at Freescale Semiconductor Inc.’s advanced-products research and development lab here. Fossum, an expert in silicon-on-insulator transistor modeling, was soon spreading the word on something he’d just learned: A planar silicon-on-insulator (SOI) transistor and a vertical double-gate device can have "pretty much the same threshold voltage." His imagination piqued by Fossum’s pronouncement, Leo Mathew, a research scientist with Freescale’s novel-structures group, proposed a transistor with a silicon channel structure resembling a T turned on its head. This week, at the International Electron Devices Meeting, Mathew will present the inverted-T field-effect transistor (ITFET), which he said appears to combine the best aspects of today’s planar transistors and tomorrow’s double-gate devices. Because the vertical and horizontal channels can be made to have nearly the same threshold voltage, they can be made to turn on simultaneously and act as a single unit, Mathew said. Freescale has yet to make complex circuits with the new device. But early tests on SRAM bit cells indicate the ITFET resolves the scaling problems confronting planar CMOS, such as the short-channel effect, while avoiding key manufacturing problems facing the tall, thin, vertical transistors known as FinFETs, said Bich-Yen Nguyen, a Freescale research manager. Ultrasmall planar CMOS devices increasingly suffer from the short-channel effect, in which the drain, rather than the gate, takes control of the channel — an issue linked to dopant fluctuations. Also, planar CMOS devices leak current through the thin gate oxide. The leakage problem is likely to remain unresolved until a high-k dielectric is inserted — and that move has been pushed back to the 32-nanometer node, expected to come on stream late this decade for high-performance devices. FinFETs address planar CMOS’ problems to an extent by wrapping a gate around a pillar of silicon. With gates on two sides sharing the electrostatic field, a slightly thicker gate oxide can be used to limit leakage, and the double- or triple-sided gate has better control over the channel, Nguyen said. From a manufacturing perspective, however, it is difficult to define a FinFET’s tall, thin structure lithographically, and the etching and cleaning steps have proved a bear to accomplish without damage, she said. A structure that seems fine for a few transistors can make for a low-yielding wafer when billions of FinFETS are involved, Nguyen said. And with FinFET performance depending in part on how thin the vertical fin can be made, companies have struggled with manufacturing controls, including the dopant implant steps, Nguyen said. Making the silicon surface smooth has required improvements in the reoxidation and anneal steps. FinFETs with 20-nm-thick fins cannot withstand ultrasonic cleaning, and cleaning often results in undercuts at the bottom of the pillars that "can cause the finlike structure to topple over," she said. Also, real-world transistors are not all the same size. In SRAM memory arrays as well as in many logic and I/O circuits, some planar transistors are made wider than the standard dimension in order to carry more current. While varying the width is straightforward with a horizontal channel, making the equivalent of a wider transistor with conventional FinFETs involves adding a second fin. In a six-transistor SRAM, for example, adding a second fin to the NMOS transistors would waste die area, Fossum said, because the second fin must be built according to the lithographic pitch, with wasted space between the fins. While the "width" of FinFETs is "digital" in that driving more current requires one, two or more fins on the pitch (line and space), the effective width of an ITFET can be varied by widening the horizontal section of the channel. That characteristic, Fossum said, "is especially useful in circuits requiring device ratioing, such as SRAMs." Fossum described the ITFET as a hybrid device, with attributes of a double-gated FinFET and a planar, fully depleted MOSFET. Mathew said the ITFET provides "far more width per unit area because both the vertical and horizontal regions are used." Simulations have shown that ITFET-based SRAMs can work with operating voltages as low as 0.6 volt, with good signal-noise margins, he said. Companies such as IBM Corp. are investigating ways to combine, on the same chip, areas of silicon with different surface orientations, taking advantage of the higher hole mobility in 110-oriented silicon for the PMOS devices and the higher electron mobility in 100 silicon in the NMOS regions. Mathew said Freescale has made ITFETs with hybrid orientation technology, creating a vertical channel with 110-oriented silicon and a horizontal silicon area with 100 silicon. "We can make [the vertical and horizontal regions] the same or different," Mathew said. "It depends how far we want to extend the areas, which depends on the application." Nguyen said the PMOS transistor performance for the Freescale structure is nearly equal to the NMOS. "With the 110 surface orientation, we have a very strong PMOS device," she said. Several process-oriented innovations came into play in learning to make the ITFET, Mathew said. The fully depleted transistor is built on a buried-oxide layer that in its first iteration is 200 nm thick, with a vertical silicon fin that is 100 nm high, connected to a horizontal silicon channel of 10 nm. "This is all one piece of silicon," Mathew said, "which gives us an advantage. We can make a self-aligned gate, and both sides are exactly the same because we do not use any specific masking step to align one side of the gate to the other." The fin is defined and etched, with further trimming accomplished by oxidation and cleaning steps. While some companies in Japan and elsewhere have developed so-called nano-CMP equipment to polish down the silicon fin, Nguyen said, Freescale devised a selective etch step that it contends is less expensive and more controllable. "It has to be a reproducible etch, with oxidation techniques to make the silicon even thinner. Those steps can be consistently controlled, which is why we think this process is far more manufacturable that what we know of other companies’ FinFET processes," she said. At his planned IEDM presentation in Washington later this week, Mathew will detail a device that has a heavily doped channel. The goal, however, is to create an ITFET with an undoped channel, which could provide higher mobility. "We are proceeding with the undoped version because that is what we will use in the future," he said. The ITFET also would gain from incorporating a metal gate electrode, high-k dielectric, hybrid orientation and other advances being planned for planar CMOS devices, he said. Vertical integration?
Moreover, Freescale could combine the ITFET with another form of vertical transistor: the multiple-independent-gate FET. The MigFET, which has been presented at various conferences over the past two years, includes aligned but separate gates on each side of the vertical channel. For certain RF and mixed-signal applications, Mathew said, the threshold voltage of each gate on a double-gated MigFET could be controlled independently and dynamically. Each gate of the MigFET could be controlled separately, with the Vt set dynamically for high-drive-current or low-power operation, Mathew said. Moving from planar to any form of vertical transistor would require a large infrastructure effort, with changes to circuit models, libraries and EDA tools, noted Bill Holt, vice president in charge of logic technology development at Intel Corp.’s Hillsboro, Ore., facility. Intel continues to work on its Tri-gate structure, in which a somewhat shorter vertical channel is surrounded on three sides by a continuous gate electrode. Holt said some people underestimate the challenge of source-drain resistance, which he said can be substantial in vertical transistors. Mark Bohr, a senior fellow at Intel, said researchers at Hillsboro have come up with a way to create a fully depleted transistor on a bulk, or non-SOI, substrate. He declined to provide details. Mathew, who has worked on vertical transistors for six years, said he believes planar CMOS "already is running into scaling limits for low-power applications because of leakage. Personally, I think the ITFET is the transistor of the future."
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