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Washington, D.C. — Intel Corp. faced off against the alliance of Advanced Micro Devices and IBM on the stage of the International Electron Devices Meeting here Tuesday (Dec. 6th), presenting 65-nm transistors that rely heavily on strained silicon to achieve sharp performance gains. Intel is in production with several 65-nm processors now, creating an inventory of commercial microprocessor products that will begin shipping early next year. At the IEDM conference, Intel showed die photos of four dual-core microprocessors using 65-nm design rules, which include the Yonah mobile processor and a desktop processor code-named Cedarmill. Sunit Tyagi, senior engineering manager at Intel Technology India (Bangalore, India) presented a 65-nm transistor that achieves a 37 percent performance improvement compared with the 90-nm technology, with a ring oscillator delay of 4.25 picoseconds. Intel made remarkably few changes at the 65-nm node, other than enhancing the germanium content in the deposited SiGe regions at the source and drain region of the PMOS device. The embedded SiGe creates a compressive stress on the PMOS transistor which produces a 30 percent improvement over Intel’s 90-nm PMOS transistor. Tyagi said Intel did not add a compressive nitrde capping over the PMOS transistor, as AMD and IBM do. Intel decided to keep its process as simple as possible in order to keep costs under control, he said, adding that “we achieved our performance goals with this approach.” Andy Wei, a member of the technical staff based at AMD Dresden, described a new process that AMD will first retrofit into its 90-nm microprocessors, and then use in its 65-nm designs going into production in the second half of next year at AMD’s new 300-mm fab in Dresden. IBM will use the new process for its initial 65-nm processors, said Gary Bronner, an IBM project leader at the IBM-AMD alliance based in East Fishkill, N.Y. “Strain engineering has replaced gate oxide scaling as the means to improve performance, because of leakage considerations at the gate,” Wei told a crowd of several hundred at a Tuesday IEDM session. AMD and IBM last year used a dual-stress-liner approach for their 90-nm transistors, putting differently configured nitride capping layers on top of the NMOS and PMOS transistors. At the 65-nm node, the partners added an embedded SiGe layer similar to what Intel used at the 90-nm node. Wei said “a big boost came when we added the embedded SiGe” at the source and drain regions of the PMOS transistor. The PMOS devices now run almost as fast as the NMOS transistors. Wei said the new process will allow design engineers to better balance the size of the N- and PMOS transistors to achieve performance improvements at the product level that he said could approach 50 percent.
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