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LONDON ?Icera Inc., a fabless semiconductor startup developing processors for wireless communications, has revealed details of its first processor core, called DXP and its first chip, which it calls Livanto. Icera (Bristol, U.K.) has been supplying the 3G processor to select customers since September, part numbered ICE8020, and the chip is now on general availability, the company said Livanto has been designed to support the sorts of algorithms used in high-speed communications while retaining software programmability without sacrificing power efficiency. It is based on a processing core called DXP and this should allow the processor to continue to be used as additional interface standards are brought onboard 3G mobile phone handsets and for future wireless standards for next generation multimode wireless terminals and handsets. The processor supports HSDPA ((High Speed Downlink Packet Access) in software through a combination of conventional processing, SIMD extensions and long instruction word processing. 揟his is not a general purpose processor but it is very good at the algorithms and operations that are prevalent in these types of processing,?said Nigel Toon, vice president of sales and marketing at Icera. Toon said that customer reports had showed Icera that it was achieving three times the performance rival solutions in typical channel conditions at similar power consumption. DXP stands for deep execution processor, although Toon declined to discuss the depth of the processing pipeline. One feature is that atomic operations can be put together in original combinations within the pipe, Toon said. The ICE8020 contains two die in a single package. The main digital chip is built for Icera in a 90-nm manufacturing process by Taiwan Semiconductor Manufacturing Co. Ltd. The second die is a mixed-signal RF interface device built in 0.18-micron CMOS process. Icera has worked with Infineon Technologies AG to offer complete boards including an RF section, Toon said Livanto has been designed to include dynamic voltage scaling and advanced clock gating, to further save power. Livanto also supports a range of external memory interfaces including NAND, NOR, SDRAM, PSRAM and mobile DDR. For communication with other chips in a system, it delivers support for MIPI抯 HSI applications processor interface, as well as a range of standard serial interfaces. In addition, Livanto?supports both single and dual antenna RF systems, via analog and digital interfaces and includes a direct SIM interface with on-chip transceivers. Icera has worked with TTPcom on developing the 3G protocol to support HDSPA and so an supply this along with the processor, Toon said. 揂fter three years of intense development, we are delighted to announce general availability of our first chip, Livanto. It抯 the first time out for the new DXP processor, easily the world抯 highest performance generic processor. Our first chips are fully functional and meet or beat all speed and yield specifications. We have designed Livanto so we can eat all processing requirements for multi-megabit data rates, both downlink and uplink, yet still offer the lowest power consumption in the industry, all from a fully flexible solution. Not surprisingly we have huge interest from terminal OEMs and operators alike,?said Stan Boland, president and chief executive officer of Icera in a statement. (() | 
