 |
|
TMS320F243的编程例子 |
|
/*****************************************************************************/
/* Testprogram for digital I/O on Port D */
/* running on TMS320F243 EVA-Board, PLL is fixed to multiply by 4 */
/* external clock is 5MHz, internal then 20Mhz */
/* date : 07/11/2000 , (C) Frank.Bormann@fh-zwickau.de */
/*****************************************************************************/
/* digital I/O on Port D0...D7 */
/* 8 LED's connected to Port D0...D7 ; LED-on : 1 LED off : 0 */
/* 'Knight-rider' : 1 of 8 LEDs switched on, then go from left to right */
/* software delay loop */
/* program-name : LED243C.c / project : F243LED */
/*****************************************************************************/
#include "regs243.h"
/************* SETUP for the OCRA - Register ***************************/
#define OCRA15 0 /* 0 : IOPB7 1 : TCLKIN */
#define OCRA14 0 /* 0 : IOPB6 1 : TDIR */
#define OCRA13 0 /* 0 : IOPB5 1 : T2PWM */
#define OCRA12 0 /* 0 : IOPB4 1 : T1PWM */
#define OCRA11 0 /* 0 : IOPB3 1 : PWM6 */
#define OCRA10 0 /* 0 : IOPB2 1 : PWM5 */
#define OCRA9 0 /* 0 : IOPB1 1 : PWM4 */
#define OCRA8 0 /* 0 : IOPB0 1 : PWM3 */
#define OCRA7 0 /* 0 : IOPA7 1 : PWM2 */
#define OCRA6 0 /* 0 : IOPA6 1 : PWM1 */
#define OCRA5 0 /* 0 : IOPA5 1 : CAP3 */
#define OCRA4 0 /* 0 : IOPA4 1 : CAP2/QEP2 */
#define OCRA3 0 /* 0 : IOPA3 1 : CAP1/QEP1 */
#define OCRA2 0 /* 0 : IOPA2 1 : XINT1 */
#define OCRA1 0 /* 0 : IOPA1 1 : SCIRXD */
#define OCRA0 0 /* 0 : IOPA0 1 : SCITXD */
/*****************************************************************************/
/************* SETUP for the OCRB - Register ***************************/
#define OCRB9 0 /* 0 : IOPD1 1 : XINT2/EXTSOC */
#define OCRB8 1 /* 0 : CKLKOUT 1 : IOPD0 */
#define OCRB7 0 /* 0 : IOPC7 1 : CANRX */
#define OCRB6 0 /* 0 : IOPC6 1 : CANTX */
#define OCRB5 0 /* 0 : IOPC5 1 : SPISTE */
#define OCRB4 0 /* 0 : IOPC4 1 : SPICLK */
#define OCRB3 0 /* 0 : IOPC3 1 : SPISOMI */
#define OCRB2 0 /* 0 : IOPC2 1 : SPISIMO */
#define OCRB1 1 /* 0 : BIO 1 : IOPC1 */
#define OCRB0 1 /* 0 : XF 1 : IOPC0 */
/*****************************************************************************/
/************* SETUP for the WDCR - Register ***************************/
#define WDDIS 1 /* 0 : Watchdog enabled 1: disabled */
#define WDCHK2 1 /* 0 : System reset 1: Normal OP */
#define WDCHK1 0 /* 0 : Normal Oper. 1: sys reset */
#define WDCHK0 1 /* 0 : System reset 1: Normal OP */
#define WDSP 7 /* Watchdog prescaler 7 : div 64 */
/*****************************************************************************/
/************* SETUP for the SCSR - Register ***************************/
#define CLKSRC 0 /* 0 : intern(20MHz) */
#define LPM 0 /* 0 : Low power mode 0 if idle */
#define ILLADR 1 /* 1 : clear illegal address bit */
/*****************************************************************************/
/************* SETUP for the WSGR - Register ***************************/
#define BVIS 0 /* 10-9 : 00 Bus visibility OFF */
#define ISWS 0 /* 8 -6 : 000 0 Waitstates for IO */
#define DSWS 0 /* 5 -3 : 000 0 Waitstates data */
#define PSWS 0 /* 2 -0 : 000 0 Waitstaes code */
/*****************************************************************************/
unsigned int LED[8]={0xFF01,0xFF02,0xFF04,0xFF08,0xFF10,0xFF20,0xFF40,0xFF80};
/* lookup table for Port D */
unsigned char n;
extern _out_wsgr();
void wait(void)
{
unsigned int i;
for(i=0;i<65000;i++);
}
void c_dummy1(void)
{
while(1); /* Dummy ISR used to trap spurious interrupts */
}
void main(void)
{
asm (" setc INTM"); /* Disable all interrupts */
asm (" clrc SXM"); /* Clear Sign Extension Mode bit */
asm (" clrc OVM"); /* Reset Overflow Mode bit */
asm (" clrc CNF"); /* Configure block B0 to data mem. */
out_wsgr((BVIS<<9)+(ISWS<<6)+(DSWS<<3)+PSWS);
/* external Function to access WSGR */
WDCR=((WDDIS<<6)+(WDCHK2<<5)+(WDCHK1<<4)+(WDCHK0<<3)+WDSP);
/* Initialize Watchdog-timer */
SCSR = ((CLKSRC<<14)+(LPM<<12)+ILLADR); /* Initialize SCSR */
OCRB = ((OCRB9<<9)+(OCRB8<<8)+
(OCRB7<<7)+(OCRB6<<6)+(OCRB5<<5)+(OCRB4<<4)+
(OCRB3<<3)+(OCRB2<<2)+(OCRB1<<1)+OCRB0);
/* Initialize output control register B */
OCRA = ((OCRA15<<15)+(OCRA14<<14)+(OCRA13<<13)+(OCRA12<<12)+
(OCRA11<<11)+(OCRA10<<10)+(OCRA9<<9)+(OCRA8<<8)+
(OCRA7<<7)+(OCRA6<<6)+(OCRA5<<5)+(OCRA4<<4)+
(OCRA3<<3)+(OCRA2<<2)+(OCRA1<<1)+OCRA0);
/* Initialize output control register A */
while(1){
for(n=0;n<14;n++){
if(n<7) PDDATDIR = LED[n];
else PDDATDIR=LED[14-n];
wait();
}
}
} () |
|
|
|
|
|
|
| |
|
|
|
|
|
|
